2007

Qu, Yang

Dynamically reconfigurable hardware (DRHW) not only has high silicon reusability, but it can also deliver high performance for computation-intensive tasks. Advanced features such as run-time reconfiguration (RTR) allow multiple tasks to be mapped onto the same device either simultaneously or multiplexed in time domain. This new type of computing element also brings new challenges in the design process. Design supports at the system level are needed. In addition, the configuration latency and the configuration energy involved in each reconfiguration process can largely degrade the system performance. Approaches to efficiently manage the configuration processes are needed in order to effectively reduce its negative impacts. In this thesis, system-level supports for design of DRHW and various configuration management approaches for reducing the impact of configuration overhead are presented. Our system-level design supports are based on the SystemC environment. An estimation technique for system partitioning and a DRHW modeling technique are developed. The main idea is to help designers in the early design phase to evaluate the benefit of moving some components from fixed hardware implementation to DRHW. The supports have been applied in a WCDMA case study. In order to efficiently apply the multi-tasking feature of DRHW, we have developed three static task scheduling techniques and a run-time scheduling technique. The static schedulers include a list-based heuristic approach, an optimal approach based on constraint programming and a guided random search approach using a genetic algorithm. They are evaluated using both random tasks and real applications. The run-time scheduling uses a novel configuration locking technique. The idea is to dynamically track the task status and lock the most frequently used tasks on DRHW in order to reduce the number of reconfigurations. In addition, we present two novel techniques to reduce the configuration overhead. The first is configuration parallelism. Its idea is to enable tasks to be loaded in parallel in order to better exploit their parallelism. The second is dynamic voltage scaling. The idea is to apply low supply voltage in reconfiguration process when possible in order to reduce the configuration energy.